1. Field of the Invention
The invention relates to a clock generating apparatus suitable for use in electronic equipment having a communicating function based on, for example, an IEEE1394 serial interface system or the like.
2. Description of the Related Art
At present, a serial interface system called IEEE1394 has been proposed as a peripheral interface of the next generation for coupling a personal computer and each commercially available equipment in correspondence to the realization of multimedia. An application to a video camera, a printer, a musical instrument, a system such as LAN in a home, or the like is being progressed by using the interface system.
In the commercially available equipment or the like, a problem of electromagnetic noises is restricted by each safety reference. In digital equipment it which a high processing speed has been realized, therefore, a spread spectrum clock is used as a method of reducing the electromagnetic noises. Specifically speaking, a jitter is generated by purposely adding noises lest a peak of a spectrum is generated at a specific frequency, or a frequency is gently fluctuated at such a frequency that no influence is exerted on the operation of a circuit, for example, at a frequency in a range from several kHz to several 100 kHz.
In a serial communication using the IEEE1394 or the like, however, in an LSI chip of a physical layer which actually handles serial communication on a cable, a precision in a range from about 50 ppmw to about 100 ppm is usually required as a frequency precision for guaranteeing the communication, so that a clock frequency cannot be gently fluctuated.
FIG. 1 shows an example of a construction of a serial communication system. As shown in FIG. 1, an LSI chip 101 of a physical layer exists between an LSI chip 102 as a link layer and a transmission line as a physical medium. The LSI chip 101 executes transmission and reception of packet data in parallel to the LSI chip 102 of the link layer on the basis of the frequency obtained by frequency dividing a clock for serial communication. Specifically speaking, in case of IEEE1394, parallel data of maximum 8 bits at 50 MHz is transmitted at a CMOS level (3V or 5V). On the transmission line side of the LSI chip 101, serial communication is performed at a rate of 400 Mbps through a terminal 103.
As mentioned above, on the parallel communication side, since an amplitude-is large and the frequency is high, it is necessary to at least take into consideration the electromagnetic noises by paying attention to this portion. That is, conditions such that while supplying a high precision clock to the serial communication side, on the parallel communication side, the spread spectrum clock is used and a clock synchronized with the clock on the serial communication side can be supplied are necessary in a chip for performing both serial communication and parallel communication. Although the use of a conventional forming circuit of the spread spectrum clock is considered to meet such a requirement, in this case, since it is necessary to change the frequency of the clock by an amount that is equal to or larger than about a few % of the ordinary frequency, it is difficult to use such a forming circuit for the chip for performing both serial communication and parallel communication.
Although a method of fluctuating only a phase without varying a frequency by a DLL (Delay-Locked Loop) has been proposed, also in this case, since an analog circuit is used, not only it is difficult to design but also there is a problem in terms of an increase in circuit area and a processing portability.
It is, therefore, an object of the invention to provide a clock generating apparatus in which a synchronized spread spectrum clock in a predetermined phase difference can be formed by a simple construction and which can be used for a chip for performing both serial communication and parallel communication.
To solve the above problem, according to the invention, there is provided a clock generating apparatus in a communication system for performing data communication between electronic equipment connected by a bus, comprising: clock forming means for forming clock signals of m (m: natural number of 2 or more) phases mutually having a phase difference; selecting means for sequentially selecting one of the clock signals of m phases which are supplied from the clock forming means and outputting it as a second clock signal; and control means for supplying a control signal to the selecting means and controlling so that a spectrum of the second clock signal obtained from the selecting means is spread.
According to the invention, the clock forming means, selecting means, and control means are provided. In the clock forming means, the m-phase clock signals whose phases are mutually deviated by a predetermined amount at a desired frequency are formed, and the clock signals of m phases formed by the clock forming means are supplied to the selecting means. The control signal is supplied from the control means to the selecting means. One of the clock signals of m phases is sequentially selected by the selecting means in response to the-control signal from the control means. Thus, the phase fluctuates forward and backward with a predetermined relation within a range of a precision permitted by a communication system as a supplying destination. The second clock signal in which the peak on the spectrum is spread is outputted from the selecting means.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.